3D Directed Self-Assembly for Nanostructures

ABSTRACT

A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/909,448, filed on Oct. 2, 2019 which application is herebyincorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to semiconductor processing, andin particular embodiments, to methods for 3D directed self-assembly fornanostructures.

BACKGROUND

Generally the fabrication of integrated circuits (IC) requires theformation of numerous device elements onto a semiconductor substrate. Inthe manufacture of IC's, various fabrication processes are executed suchas film-forming depositions, etch mask creation, patterning, materialetching and removal, and doping treatments. These processes areperformed repeatedly to form structures for circuit components andinterconnect elements (e.g. transistors, resistors, capacitors, metallines, contacts, and vias). Historically, with microfabrication,transistors have been created in one plane, with wiring/metallizationformed above the active device plane, and have thus been characterizedas two-dimensional (2D) circuits or 2D fabrication.

At each successive technology node, the sizes of IC device elements areshrunk to roughly double the component packing density. These scalingefforts have greatly increased the number of circuit elements andinterconnect elements per unit area of a 2D circuit. As these scalingefforts are entering single digit nanometer technology nodes, it isbecoming increasingly more challenging to achieve the required packingdensity using 2D fabrication.

Three-dimensional (3D) circuits or 3D fabrication has been identified asan alternative method to form more densely packed devices. 3Dintegration overcomes scaling limitations of 2D circuits by increasingdevice elements density in volume rather than area by verticallystacking multiple devices. However, 3D circuits have their ownadvantages and disadvantages. While 3D circuits have been successfullydemonstrated with 3D NAND, 3D integration of logic devices brings aunique set of challenges.

SUMMARY

In accordance with an embodiment of the present invention, a method forforming a device includes receiving a substrate having nano-channelspositioned over the substrate and extending in a direction parallel to aworking surface of the substrate, the nano-channels arranged so thatfirst nano-channels are positioned vertically above second nano-channelsin a vertical stack, the nano-channels having a gate formed all around across section of the nano-channels; depositing a polymer mixture on thesubstrate that fills open spaces around the nano-channels; causingself-assembly of the polymer mixture resulting in forming polymercylinders extending parallel to the working surface of the substrate andperpendicular to the nano-channels; and metalizing the polymer cylinderssufficient to create an electrical connection to terminals of thenano-channels.

In accordance with an embodiment of the present invention, a method forforming a device includes receiving a substrate having a threedimensional (3D) structure including a plurality of nano-sheets, aplurality of walls, and a plurality of cavities, one of the plurality ofnano-sheets including a first sheet separated from a second sheet of theplurality of nano-sheets in a first direction by one of the plurality ofcavities, the plurality of nano-sheets being supported by the pluralityof walls, the plurality of nano-sheets extending along a seconddirection orthogonal to the first direction, the first sheet beingspaced apart from a third sheet of the plurality of nano-sheets along ahorizontal plane in a third direction that is orthogonal to both thefirst and the second directions; and forming a plurality of cylindricalinterconnects within the 3D structure with a directed self assemblyprocess, where each of the plurality of cavities includes one of theplurality of cylindrical interconnects.

In accordance with an embodiment of the present invention, a method forforming a device includes forming a first stack of plurality ofnano-lines over a substrate, the first stack of plurality of nano-linesincluding first nano-lines arranged in a first plane above the substrateand second nano-lines arranged in a second plane above the first plane;and forming a first set of polymer cylinders between the firstnano-lines and the second nano-lines with a first directed self-assemblyprocess.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1A-1F illustrate cross-sectional views of a semiconductor deviceduring various stages of fabrication in accordance with an embodiment ofthe present application, wherein FIG. 1A illustrates a cross-sectionalview of a 3D device, FIG. 1B illustrates a top view of the 3D deviceillustrated in FIG. 1A, FIG. 1C illustrates a cross-sectional view ofthe 3D device after coating with a self-assembling polymer mixture, FIG.1D illustrates a cross-sectional view of the 3D device after causingself-assembly of the polymer mixture in order to form a pattern ofinterconnects, FIG. 1E illustrates a cross-sectional view of the 3Ddevice after an optional step of selectively etching the pattern ofinterconnects, and FIG. 1F illustrates a cross-sectional view of the 3Ddevice after metalizing the pattern of interconnects to form functionalinterconnects;

FIG. 2 is a flow chart illustrating an example process flow of a processused to form interconnects within a 3D integrated device in accordanceto an embodiment of the present application;

FIGS. 3A-3B illustrate cross-sectional views of a semiconductor deviceduring various stages of fabrication in accordance with an embodiment ofthe present application, wherein FIG. 3A illustrates a cross-sectionalview of the device after forming a first nano-sheet with a respectivefirst set of interconnects, and FIG. 3B illustrates a cross-sectionalview of the device after forming a second nano-sheet and a respectivesecond set of interconnects;

FIGS. 4A-4D illustrate cross-sectional views of a semiconductor deviceduring various stages of fabrication in accordance with an embodiment ofthe present application, FIG. 4A illustrates a cross-sectional view ofthe device after forming a second stack of nano-sheets over the firststack of nano-sheets, FIG. 4B illustrates a cross-sectional view of thedevice after coating the device with a second self-assembling polymermixture, FIG. 4C illustrates a cross-sectional view the device aftercausing self-assembly of the second polymer mixture in order to form asecond pattern for interconnects, and FIG. 4D illustrates across-sectional view of the device after metalizing the second patternof interconnects to form functional interconnects;

FIG. 5 is a flow chart illustrating an example process flow of a processused to form interconnects within a 3D integrated device comprisingmultiple stacks of nano-sheets using two directed-self assemblyprocesses in accordance to an embodiment of the present application;

FIG. 6 illustrates a cross-sectional view of a semiconductor deviceduring a stage of fabrication in accordance with an embodiment of thepresent application, wherein FIG. 6 illustrates a cross-sectional viewof the device after orthogonal interconnects are formed over stacks ofnano-sheets; and

FIGS. 7A-7B illustrates cross-sectional views of a semiconductor deviceduring a stage of fabrication in accordance with an embodiment of thepresent application, wherein FIG. 7A illustrates a top view of thedevice after interconnects are routed between different vertical stacksof nano-sheets or nano-wires across the working surface of thesubstrate, and FIG. 7B illustrates a cross-sectional view of an upwardangled interconnect.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

As previously mentioned, a vertical stack design of 3D integrateddevices offers an increase in packing density. However, 3D integrationhas a number of engineering difficulties arising from the verticality of3D device structures. This disclosure describes embodiments of methodsto mitigate some of those issues.

3D integration overcomes scaling limitations of 2D circuits byincreasing device elements density in volume rather than area byvertically stacking multiple devices. One disadvantage of verticallystacking device elements is that it creates obstacles because theterminals of device elements are not accessible from the top surface ofthe device. This is especially problematic when forming interconnectsbetween device elements. One issue when forming interconnects is thatconventional interconnect development processes are top-down processes.For example, interconnect structures such as holes for contacts or viasare formed by vertical etching, as understood by those with ordinaryskill in the art. This is acceptable for forming interconnections of a2D device because the terminals of each device element are accessiblefrom above the substrate. In the case of a 3D device, device elementsare stacked vertically and the terminals of every device element are notaccessible from the top of the device and interconnects may have to berouted horizontally between device elements in vertical layers.Therefore, an interconnect development process that can form horizontalinterconnections between vertical layers can ease the difficulties ofinterconnecting 3D structures.

Another issue with 3D integration is the metallization of interconnects.Typically interconnect features, such as holes for contacts or vias, aremetalized by depositing metal into the etched holes using a conventionaltop-down method. In the case of 3D integration, as discussed above, theinterconnect structures are routed vertically and cannot be metalizedusing a conventional top down metallization process.

Embodiments of the present invention advantageously overcome the aboveissues by forming interconnections using directed-self assembly whichallows for the formation of horizontally routed interconnects betweenvertically stacked device elements. Accordingly, one or more embodimentswill be described using the cross-sectional FIGS. 1A-1F along with theflow chart of FIG. 2. Further embodiments of forming interconnects usinga directed-self assembly will be described using FIGS. 3-7.

FIGS. 1A-1F illustrate cross-sectional views of a semiconductor deviceduring various stages of fabrication in accordance with an embodiment ofthe present application.

FIG. 1A illustrates a cross-sectional view of an example 3D integrateddevice and FIG. 1B illustrates a top view of the 3D device illustratedin FIG. 1A. In this illustrative embodiment, the 3D integrated device isa gate-all-around transistor. The 3D integrated device may includevertically stacked structures comprising nano-sheets or nano-wires thatmay be used to form logic devices such as a complementary metal oxidesemiconductor (CMOS) device, memory devices such as a NAND or NORmemory.

In one illustrated embodiment, the nano-sheets (nano-wires ornano-channels when the width of the sheets is in the nanometer regime)comprise a second nano-sheet 104 vertically stacked over a firstnano-sheet 102 formed over an insulating layer 108 formed over asubstrate 110. The insulating layer 108 may comprise an insulating oxidematerial such as silicon oxide or silicon dioxide and may furtherinclude other dielectric materials such as silicon nitride. Thesubstrate no may be a bulk substrate such as a bulk silicon substrate, asilicon on insulator substrate, or various other semiconductorsubstrates including a germanium substrate, a silicon carbide substrate,a gallium nitride substrate, a gallium arsenide substrate, and others.

In various embodiments, the first nano-sheet 102 may comprise aplurality of a first type of transistors and the second nano-sheet 104may comprise a plurality of second type of transistors. In one or moreembodiments, the first type of transistors may be a gate all aroundfield effect transistor, a non-volatile memory such as a NAND or NORmemory, transistor or capacitors used in a volatile memory such as SRAM,DRAM, and others. Similarly, in one or more embodiments, the second typeof transistors may be a gate all around field effect transistor, anon-volatile memory such as a NAND or NOR memory, transistor orcapacitors used in a volatile memory such as SRAM, DRAM, and others.

In one example, the first nano-sheet 102 may comprise a plurality ofn-type MOS devices and the second nano-sheet 104 may comprise aplurality of p-type MOS devices. In another example, the firstnano-sheet 102 may comprise a plurality of p-type MOS devices and thesecond nano-sheet 104 may comprise a plurality of n-type MOS devices.The first nano-sheet 102 and the second nano-sheet 104 are positionedover the substrate in a manner such that the first nano-sheet 102 andthe second nano-sheet 104 extend in a direction parallel to a workingsurface of the substrate. In various embodiments, the first nano-sheet102 may be vertically stacked above the second nano-sheet 104.

The first nano-sheet 102 and the second nano-sheet 104 may extend in ahorizontal direction and are supported by gates 106 physically wrappedaround the first nano-sheet 102 and the second nano-sheet 104. The gates106 may comprise polysilicon, titanium nitride, and/or other metallicmaterials known to a person having ordinary skill in the art.

The first nano-sheet 102 and the second nano-sheet 104 extend betweenthe gates 106, forming a plurality of cavities 112 in the form oftrenches bookended by adjacent pairs of gates 106, and nano-channels ateach intersection between the nano-sheets and the gates 106. Also, a setof outer spaces 113 are formed where the first nano-sheet 102 and thesecond nano-sheet 104 extend past the outer gates 106 and where thegates 106 extend above the second nano-sheet 104. The first nano-sheet102 and the second nano-sheet 104 are separated vertically by theplurality of cavities 112. The plurality of cavities 112 extend in adirection orthogonal to the first nano-sheet 102 and the secondnano-sheet 104 and oriented parallel to the gates 106.

As understood by those with ordinary skill in the art, the firstnano-sheet 102 and the second nano-sheet 104, or nano-wires in otherembodiments, may be formed by forming an alternating series of activeand sacrificial layers, patterning the alternating layers intoindividual nano-sheets or nano-wires corresponding to differentfield-effect transistors (FET), and then removing the sacrificial layersselective to the active layers after patterning. The active andsacrificial layers may comprise of two different layers that can beselectively etched to one another as alternating layers. For example theactive layers may be selected to be a material selected from groupsIII-V of the periodic table and the sacrificial layer may be selected tobe a material from groups II-VI of the periodic table.

The nanoscale transistor channels formed by the intersection ofnano-sheets (nano-wires or nano-lines) with the gates 106 may havevarious cross-sectional shapes such as circular, rectangular, or square,and may have rounded edges. The first and the second nano-sheets 102 and104 may be isolated from the gates 106 by a gate dielectric such assilicon oxide, silicon oxynitride, hafnium based oxide, or others andmay comprise of any material and may be formed in any manner known bythose with ordinary skill in the art. In one embodiment, the gates 106wrapped around the first nano-sheet 102 and the second nano-sheet 104have outer side walls having discrete sides. In other embodiments, thegates 106 wrapped around the nano-sheets may have circular outer sidewalls. The inner walls of the gates 106 contacting the gate dielectricmay be formed in any suitable shape, for example, rectangular, circularor substantially circular.

Although FIG. 1A illustrates a single vertically stacked structure oftwo complimentary nano-sheets, multiple nano-sheets may be stacked toform a 3D integrated device.

FIG. 1B illustrates a top down view of the 3D integrated device. Asillustrated in FIG. 1B, multiple vertically stacked structures may beformed adjacent to each other. As illustrated in FIG. 1B, additionalvertically stacked structures comprising a second nano-sheet 104 formedover a first nano-sheet 102 may be formed adjacent to each other acrossa horizontal plane formed by the working surface of the substrate 114.For example, each horizontal plane may include a plurality ofnano-sheets such as a plurality of first nano-sheets 102 in a firstplane and a plurality of second nano-sheet 104 in a second plane abovethe first plane.

As illustrated in FIGS. 1A-1B, the plurality of cavities 112 extend in adirection orthogonal (e.g., into the plane of paper in FIG. 1A) to thefirst nano-sheet 102 and the second nano-sheet 104. Also, the pluralityof cavities 112 is not accessible from above the device because they areblocked by the second nano-sheet 104. Therefore, forming horizontalinterconnects with a conventional top-down interconnect developmentprocesses is difficult because of the lack of access from above thesubstrate.

Advantageously, as illustrated in FIGS. 1C-1F, a directed-self assembly(DSA) method is used to form horizontally routed interconnects betweenvertically stacked structures.

Referring to FIG. 1C, a polymer mixture 116 is coated over the substrateand fills the plurality of cavities 112 between the first nano-sheet 102and the second nano-sheet 104 and the gates 106, the plurality of outerspaces 113, and the entire working surface of the substrate 114.However, prior to coating the polymer mixture 116, a fill material 115is coated to fill the cavity between the first nano-sheet 102 and theinsulating layer 108. The fill material 115 may be the matrix material(i.e., first polymer of the polymer mixture 116) or other materials suchas a resist material, amorphous carbon containing layer, and others.Alternately, in one the fill material 115 is the same material as thepolymer mixture 116 and is applied in the same process step. In such anembodiment, the distance between the first nano-sheet 102 and theunderlying insulating layer 108 is such that no interconnect cylindricalstructures are formed between them.

In various embodiments, the polymer mixture 116 comprises a blockcopolymer comprising blocks of multiple monomers. As an illustration,the block copolymer may comprise a block of a first monomer (-A-A- . . .A-A-) and a block of a second monomer (-B-B- . . . B-B-). Accordingly,the first polymer may be formed from the first monomer (A) while thesecond polymer may be formed from the second monomer (B). In one or moreembodiments, the polymer mixture 116 is a block copolymer((-A-A-A-B-B-B-B-)-(-A-A-A-B-B-B-B-)- . . . (-A-A-A-B-B-B-B-)-). Infurther embodiments, the polymer mixture 116 may also another blockcopolymer with a different ratio of the first and the second monomers.Examples of polymers precursors used to form the block copolymer includemethyl-methacrylate, styrene, dimethylsiloxane, ethylene oxide,butadiene, vinylpyridine, isoprene, latic acid, and others.

In various embodiments, the first monomer has a first mole fraction inthe polymer mixture 116 and the second monomer has a second molefraction in the polymer mixture 116. As is known to a person havingordinary skill in the art, the chemical composition of the blockcopolymer may be tailored by varying the composition and mole fractionof the monomers to control the type of phase separation after anannealing process. During annealing, the blocks of monomers in the blockcopolymer undergo microphase separation to form a microstructurecontaining small polymer units of the first monomer and small polymerunits of the second monomer. These units of the first monomer (or firsthomopolymer) may be separated from the units of the second monomer(second homopolymer) in repeating patterns or periodic structures. Thetype of pattern may be spheres of the first homopolymer embedded in amatrix of the second homopolymer (or vice versa), hexagonal close packedcylinders of the first homopolymer embedded in a matrix of the secondhomopolymer (or vice versa), gyroid, or lamellae of alternating firsthomopolymer and second homopolymer.

As understood by those with ordinary skill in the art, the chemicalcomposition and/or the molecular weight of the polymer mixture 116 maybe tuned or formulated based on required device structure geometryincluding the critical dimension, pitch, microphase separation, volumefraction, the interaction parameter, and the degree of polymerization ofthe polymer mixture. In various embodiments, the composition of thepolymer mixture 116 is controlled so that the subsequent phaseseparation forms hexagonal close packed cylinders of the firsthomopolymer embedded in a matrix of the second homopolymer (or viceversa).

In one embodiment, the polymer mixture 116 may be intended to form acylindrical structure and may comprise apolystyrene-b-polydimethylsiloxane (PS-b-PDMS) block copolymer,polystyrene-b-polymethyl methacrylate (PS-b-PMMA) block copolymer, or apolystyrene-b-2-polyvinylpryridine (PS-P2VP) block copolymer. In variousembodiments, the polymer mixture 116 may be deposited using anyconventional means known by those with ordinary skill in the art, suchas spin-coating with a Track tool.

In one embodiment, the polymer mixture 116 is a bilayer di-blockcopolymer mixture formed by a mixture of block copolymers eachcomprising the same two polymers. In other embodiments, the polymermixture 116 may comprise a multi-block copolymer mixture such as atri-block terpolymer mixture((-A-A-A-B-B-B-B-C-C-)-(-A-A-A-B-B-B-B-C-C-)- . . .(-A-A-A-B-B-B-B-C-C-)-) formed by mixing block copolymer mixturescomprising three polymers.

In various embodiments, the polymer mixture 116 may also include asolvent in addition to the block copolymers. The solvent may be selectedto be neutral or selected such that the minority polymers of the polymermixture 116 are highly soluble in the solvent in a subsequent solventannealing step to cause self-alignment of the polymers comprising thepolymer mixture 116. Examples of solvents may include acetone, carbondisulfide, dimethylformamide, toluene, and tetrahydrofuran.

In one embodiment, the polymer mixture 116 comprises a bilayer di-blockcopolymer configured to form a first set of cylinders where eachcylinder of the first set of cylinders comprises the first polymer ofthe polymer mixture 116 surrounded by a matrix 118 comprising the secondpolymer of the polymer mixture 116 after microphase separation in asubsequent step. Therefore, in one embodiment, the second polymer(matrix material) is the majority polymer in the polymer mixture 116 andthe first polymer used to form the first set of cylinders is theminority polymer in the polymer mixture 116, as understood by those withordinary skill in the art.

In other embodiments, a tri-block terpolymer, such aspolyisoprene-b-polystyrene-b-polylactide, may be configured to form afirst set of cylinders comprising a first minority polymer and a secondset of cylinders comprising a second minority polymer that are bothsurrounded by a matrix material comprising a majority third polymer (orany combination thereof). In some embodiments, the first set ofcylinders may be dummy interconnects that intersect and terminate withrespective nano-sheets and assist in the formation of the second set ofcylinders (or vice-versa). In other embodiments, the tri-blockterpolymer may be configured to form core-shell cylinders (i.e. acylinder comprising the first polymer formed inside a cylindercomprising the second polymer in a matrix of the third polymer or anycombination thereof) in order to form thinner cylinders than a bilayerdi-block copolymer mixture.

Generally, in order to control the location and orientation of themicrophase separation of self-aligning structures in a subsequent step,guide patterns such as pinning structures are required. Advantageously,in various embodiment, the plurality of cavities 112 comprise thenano-sheets extending horizontally to the substrate and are bookended bythe gates 106, forming nano-channels at the intersection of thenano-sheets and the gates 106 that may be used as pinning structures.Advantageously, this allows for the formation of cylinders within theplurality of cavities 112 to function as interconnects without access tothe plurality of cavities 112 from above the substrate. Anotheradvantage of the nano-sheets and the gates 106 functioning as pinningstructures is that additional lithography process steps for formingpinning structures or any other guide templates can be avoided, reducingthe process time and cost.

In various embodiments, the nano-sheets may be functionalized allowingfor the formation of a rich variety of three-dimensional cylinderstructures with controllable bends, angles, and junctions based on theperiodicity of the nano-sheets. Advantageously, in various embodimentswhere the first nano-sheet 102 and the second nano-sheet 104 comprisecomplimentary transistors, the first nano-sheet 102 and the secondnano-sheet 104 are already functionalized because the transistors formedin the first nano-sheet 102 and the second nano-sheet 104 are oppositelydoped. For example, if the first nano-sheet 102 comprises nmostransistors and the second nano-sheet 104 comprises pmos transistors,the n-doping of the first nano-sheet 102 may attract the minoritypolymer of the polymer mixture 116 while the opposite doped secondnano-sheet 104 repels the minority polymer (or vice versa) due to e.g.,surface energy effects. One advantage of this is that the polymermaterial intended to form the cylinders may be attracted to one of thenano-sheets and self-align to one of the terminals of a transistor of anano-sheet in a first level and connect to a terminal of a transistor ofa nano-sheet in a vertically adjacent level. For example, a cylinderintended to function as an interconnect may self-align to a terminal ofa first transistor of the second nano-sheet 104, extend horizontally toadjacent transistors, and self-align to terminals of the same type oftransistors of the second nano-sheets 104 of adjacent transistors, andform the structure for interconnects between adjacent transistors basedon the periodicity of the nano-channels.

In various embodiments, the nano-sheets may be functionalized usingother techniques besides doping such as by using a different material,for example, silicon germanium versus silicon. For example, the pmostransistors may have silicon germanium that may be used topreferentially attract the minority polymer during microphasesegregation. Other ways to selectively functionalize may be to use amasking process to selectively cover some of the nano-sheets with asurface material, for example, using a self assembly process or adeposition process. The combination of functionalized nano-sheets withthe directed self assembly technique allows the formation of aninterconnect pattern that is much more complex. For example, ifalternating nano-sheets in a same horizontal plane are functionalizeddifferently, for example, alternating n-type and p-type regions, thecylinders thus being formed may be made to selectively contact only then-type nano-sheets skipping through the intermediate p-type nano-sheets.For example, a cylinder aligned to a terminal of a transistor of thesecond nano-sheet 104 may be routed to connect to a terminal in atransistor of a first nano-sheet 102 that is not directionally adjacentacross the horizontal plane of the working surface of the substrate 114.

Referring to FIG. 1D, the polymer mixture 116 undergoes microphaseseparation to form a self-assembling structure. For example, in oneembodiment, microphase separation may be caused by thermal annealingwhich causes the polymers that comprise the polymer mixture 116 toseparate and form a structure that may comprise repeating patterns orperiodic structures.

Thermal annealing may include hot plate annealing, furnace annealing,flash lamp based annealing, rapid thermal annealing, microwaveannealing, or any other annealing method known by one with ordinaryskill in the art. In various embodiments, the annealing may be performedbetween 50° C. to 500° C., and in one embodiment between 200° C. and400° C.

In other embodiments, solvent vapor annealing may be used to causemicrophase separation. Solvent vapor annealing first involves placingthe substrate, after it is coated with the polymer mixture 116, in achamber with a solvent atmosphere. The solvents used to form theatmosphere may be neutral or selective to one of the polymers of thepolymer mixture 116. During solvent vapor annealing the film thicknessof the polymer mixture 116 may swell to several times its initialthickness due to the ingress of solvent into the polymer mixture 116.The swelling of the polymer mixture 116 creates space between thepolymers comprising the polymer mixture 116 which increases the chainmobility of the polymer mixture 116 and may cause microphase separation(i.e. self-assembly). In other embodiments an additional quenching stepmay be required to cause microphase separation. The solvent vapor usedfor solvent annealing may comprise toluene vapor or heptane vapor, forexample.

For example, in one embodiment, after microphase separation, a first setof cylinders 120 comprising the minority first polymer are embedded in amatrix 118 comprising the majority second polymer within the pluralityof cavities 112 and the plurality of outer spaces 113.

As understood by those with ordinary skill in the art, a pinningstructure is required order to control the orientation and formationpattern of the first set of cylinders 120 or the first set of cylinderswill form in a random uncontrollable pattern referred herein as a“finger print” pattern. Therefore, as illustrated in FIG. 1D, thecylinders of the first set of cylinders 120 formed in the plurality ofouter spaces 113 are not within plurality of cavities 112, andtherefore, are outside of the pinning structure and form cylinders in arandom pattern while the cylinders of the first set of cylinders 120formed within the plurality of cavities (i.e. within the pinningstructure) form in a controllable pattern.

The first set of cylinders 120 within the plurality of cavities 112 runperpendicular to the first nano-sheet 102 and the second nano-sheet 104.The first set of cylinders may be routed to extend into adjacentcavities formed by adjacent vertical stacks of nano-sheets or nano-wiresformed in the horizontal plane across the working surface of thesubstrate and form interconnects between terminals of transistors formedin adjacent vertical stacks of nano-sheets (or nano-wires).

In various embodiments, the solvent vapor used during solvent annealingmay be selected to be highly selective to the minority polymer of thepolymer mixture 116 (i.e. the polymer that forms the first set ofcylinders 120). During solvent annealing, the solid-liquid interfacemoves vertically upward, towards the substrate-vapor interface, andpreferentially incorporates the minority polymer. Thus, the excessminority polymer curves upwards vertically past the nano-sheets intolarger agglomerates, which may be also used to form contact pads in someembodiments. The curving of the minority polymer cylinders can becontrolled by controlling the solvent annealing process parameters suchas vapor pressure and temperature of annealing in various embodiments.

Advantageously, in various embodiments, the portions of the first set ofcylinders 120 that extend out of the plurality of cavities 112 may forman elbow shape and bend upwards and even 90 degrees in one embodiment.This enables the formation of interconnects within the verticallystacked nano-sheets or nano-wires as discussed in another embodimentbelow. Advantageously, as described above, in some embodiments whereself-alignment is caused by solvent annealing, the portions of the firstset of cylinders 120 that extend horizontally past the nano-sheets maybend upwards forming a “U shape” and may provide contact between atransistor formed in the first nano-sheet 102 and a transistor formed inthe second nano-sheet 104 or to a contact pad in a upper level.

FIG. 1E illustrates removing the first set of cylinders 120 and thematrix 118 formed outside the plurality of cavities 112 and an optionalstep where the first set of cylinders 120 comprising the first polymeris removed selective to the matrix 118 comprising the second polymer.

The cylinders of the first set of cylinders 120 and the matrix 118formed outside the plurality of cavities 112 are removed in an etchingprocess in various embodiments. The subsequent etching step may comprisea combination of etching processes. A timed wet etch or a planarizationprocess may be used to remove the matrix 118 including the cylinderabove the second nano-sheet 104. This may be followed by a masked etchprocess using an anisotropic etching process to remove the matrix 118surrounding the plurality of cavities 112.

In some embodiments, unused cylinders of the first set of cylinders 120may be formed within the plurality of cavities 112 and across theworking surface of the substrate 114. These unused cylinders of thefirst set of cylinders 120 may be removed by forming an etch mask (i.e.,a cut mask) and using a lithography process to selectively remove them.

Optionally, as known to a person having ordinary skill in the art, thefirst set of cylinders 120 are removed using an isotropic wet processthat selectively removes the first polymer to form cylindrical openings121. Advantageously, in some embodiments, the first polymer and thesecond polymer of the polymer mixture 116 are controllable bysynthetically tailoring the first polymer and the second polymer whenforming the polymer mixture 116 to ensure that the etching process ismore selective to etch the first polymer than the second polymer (orvice versa in other embodiments). After the first set of cylinders 120are removed, the cylindrical openings 121 are metalized to becomefunctioning interconnects by filling them with a metal in a subsequentstep.

In other embodiments, the first set of cylinders 120 may be metalizeddirectly by infiltrating or embedding the first set of cylinders 120with a metal, making removing the first set of cylinders 120unnecessary.

Referring to FIG. 1F, structures formed between the vertical stacks ofnano-sheets are converted into functional interconnects. In someembodiments, where the first polymer comprising the first set ofcylinders 120 is removed, the structures are metalized by filling thecylindrical openings 121 using a deposition process. In one or moreembodiments, Atomic layer deposition can be used to deposit materialsfrom ALD precursors into polymer blocks with specific chemistries suchas PMMA. For example, the cylindrical openings 121 may be filled with ametal using an atomic layer deposition process (ALD), where a metal suchas platinum may be deposited using an ALD precursor.

As mentioned above, the polymer mixture 116 is formed with polymershaving specific chemistries that are selective to metal deposition inorder to metalize the first set of cylinders 120 using a depositionprocess.

In other embodiments, where the first set of cylinders 120 are notselectively removed, the interconnections may be metalized by imbeddingor infiltrating metal particles into the voids of the first set ofcylinders 120. In some embodiments, the first set of cylinders 120 maybe metalized by imbedding or infiltration using a sequentialinfiltration process (SIS), for example.

In various embodiments, the SIS process may include a plurality ofalternating exposures of the self-assembled structure to a metalprecursor compound and a reactant precursor. The metal precursorcompound may comprise trimethyl aluminum (TMA), titanium tetrachloride(TiCl₄), diethyl zinc (DEZ), or hexafluoride (WF₆). The reactantprecursor may comprise an oxygen source (e.g., H₂O, O₂, O3, H₂O₂), areducing agent (H₂, H₂S₂Si₂H₆, etc.), or other compounds reactive withthe first precursor. A purge step (e.g., N₂) may be performed followingeach precursor exposure to remove residual reactant. Exposures of eachreactant can be performed in one step or in a series of two or moresteps to control the amount of material that infiltrates the first setof cylinders 120. In various embodiments the metal precursor has anaffinity to the minority polymer of the polymer mixture 116 that formsthe first set of cylinders 120 and infiltrates the surface of theminority polymer (i.e. the surfaces of the first set of cylinders 120).The second precursor completes the reaction with the first precursorformed on the surface of the minority polymer and forms a set of firstset of metalized cylinders 123. Examples of metals formed by the SISprocess may include gold, palladium, Al₂O3, TiO₂, ZnO, SiO₂, or HfO₂,for example.

In other embodiments the first set of cylinders 120 may be metalizedusing a vapor phase infiltration process (VPI), vapor phase infiltration(VPI), or multiphase vapor infiltration (VPI), for example.

As understood by those with ordinary skill in the art, after formingfunctional interconnects a filler material 122 may be formed within theouter spaces 113 in order to isolate each vertical stack of nano-wiresor nano-sheets to prevent cross-talk between adjacent vertical stacks ofnano-wires or nano-sheets, current injections, shorting, and otherproblems. The filler material 122 may comprise an isolating oxide suchas silicon oxide, silicon dioxide, or silicon nitride and may be formedusing a local oxidization of silicon process (LOCOS) or any other methodknown in the art.

FIG. 2 is a flow chart illustrating an example process flow of a processused to form interconnects within a 3D integrated device in accordanceto an embodiment of the present application.

As illustrated in block 200 and described with reference to FIG. 1A,vertically stacked nano-sheets are formed over the substrate in adirection parallel to a working surface of the substrate, thenano-sheets having gates 106 formed all around a cross-section of thenano-sheets. A plurality of nano-channels and a plurality of cavities112 are formed by the intersection of a first nano-sheet 102 and asecond nano-sheet 104 and the gates 106. The first nano-sheet 102 andthe second nano-sheet 104 and the gates 106 may be formed as known to aperson having ordinary skill in the art, and may comprise the materialsas described in FIG. 1A.

As next illustrated in block 202, and described with reference to FIG.1C, the plurality of cavities 112 and outer spaces 113 are filled with apolymer mixture 116 that fills the open spaces.

As next illustrated in block 204, and described with reference to FIG.1D, the polymer mixture 116 undergoes self-assembly, forming a first setof cylinders 120 comprising a first polymer (minority) material of thepolymer mixture surrounded by a matrix 118 (majority polymer) of thepolymer mixture 116.

As next illustrated in block 206 and described with reference to FIGS.1E-1F, the first set of cylinders 120 are metalized, forming functionalinterconnects between the terminals of transistors formed in adjacentstacks of nano-sheets formed across the horizontal plane formed by theworking surface of the substrate 114. The first set of cylinders 120 aremetalized by either selectively removing the first set of cylinders 120,as described in FIG. 1E, and using a metal deposition process, or usingimbedding/infiltration in the same manner described in FIG. 1F. Asexplained above, the matrix 118 is removed and a filler material 122 isformed around the outer spaces 113 in order to isolate the verticalstack of nano-sheets.

FIGS. 3A-3B illustrate an alternative embodiment of the presentapplication where FIGS. 3A-3B illustrate cross-sectional views of asemiconductor device during various stages of fabrication in accordancewith an embodiment of the present application, wherein FIG. 3Aillustrates a cross-sectional view of the device after forming a firstnano-sheet with a respective first set of interconnects, and FIG. 3Billustrates a cross-sectional view of the device after forming a secondnano-sheet and a respective second set of interconnects.

Unlike the prior embodiments, in this embodiment, the interconnects areformed (or at least the pattern for interconnects without the finalmetallization) at each level before forming the next level ofnano-sheets. Accordingly referring to FIG. 3A, a first nano-sheet 102physically supported by gates 106 surrounding the first nano-sheet 102is formed over an insulating layer 108 formed over a substrate no. Thefirst nano-sheet 102, the gates 106, the insulating layer 108, and thesubstrate no may be formed as known to a person having ordinary skill inthe art and may comprise the same material described in FIG. 1A.

While the first nano-sheet 102 may be functionalized, e.g., doped toselectively attract the second polymer to form cylindrical structurescontacting the first nano-sheet 102, there is no competing surface froman overlying nano-sheet. Thus, this embodiment may be used when bothlevels of nano-sheets (i.e., first nano-sheet 102 and the to be formedsecond nano-sheet 104) are functionalized similarly, for example, bothare pmos devices or both are nmos devices.

As described in prior embodiments, after functionalizing the firstnano-sheet 102 to be attractive to a minority polymer of a firstself-aligning polymer mixture, the first self-aligning polymer mixtureis coated over the substrate no. The first self-aligning polymer mixturefills the cavities formed between the first nano-sheet 102 and the gates106 and the areas surrounding the first nano-sheet 102 and the gates 106in the same manner described in FIG. 1C. As also explained above withrespect to FIG. 1C, a fill material 115 may be coated between the cavityformed between the first nano-sheet 102 and the insulating layer 108.

After coating the substrate no with the first self-aligning polymermixture, the first self-aligning polymer mixture undergoes microphaseseparation and forms cylinders containing blocks of the minority polymerwith a matrix 118 containing blocks of a majority polymer. As explainedabove, the cylinders formed outside the plurality of cavities may beremoved while the cylinders within the plurality of cavities aremetallized to form a first set of metalized cylinders 123. One advantageof this is that the matrix 118 serves as a surface material masking thefirst nano-sheet 102 and allows for additional functionalizednano-sheets and interconnects to be formed above the first nano-sheet102 while the first nano-sheet 102 remains masked and unaffected. Thus,in this embodiment, the subsequent nano-sheet may be functionalizedsimilar to the first nano-sheet 102.

Referring to FIG. 3B, a second nano-sheet 104 physically supported bygates 106 surrounding the second nano-sheet 104 is formed over the firstnano-sheet 102. The second nano-sheet 104 and the gates 106 may beformed as known to a person having ordinary skill in the art and maycomprise the same materials formed in FIG. 1A. After forming the secondnano-sheet 104, the second nano-sheet 104 may be functionalized asdescribed in FIG. 3A. Then a second self-aligning polymer mixture iscoated over the substrate no in the same manner described in FIG. 3A. Inone or more embodiments, the second self aligning mixture may be tunedor formulated to form interconnects with a different critical dimension,pitch, microphase separation, volume fraction, interaction parameter,and the degree of polymerization than the first self-aligning polymermixture. In one embodiment, the second self-aligning mixture and thefirst self-aligning mixture may comprise the same polymers but may betuned by having a different molecular weight than the firstself-aligning polymer mixture. In one embodiment, the secondself-aligning polymer mixture may be tuned by having a differentchemical composition than the first self-aligning polymer mixture. Inone or more embodiments, the first self-aligning mixture and the secondself-aligning mixture may comprise the exact same material in order toform two sets of the cylinders having similar critical dimensions andpitch.

The second self-aligning polymer mixture fills the cavities formed byintersection of the second nano-sheet 104 and the gates 106 and theareas surrounding the second nano-sheet 104 and the gates 106 in thesame manner described in FIG. 1C. Meanwhile, the cavities formed by theintersection of the first nano-sheet 102 and the gates 106 remain maskedby the matrix material of the first self-aligning polymer mixture.

After coating the substrate no with the second self-aligning polymermixture, the second self-aligning polymer mixture undergoes microphaseseparation and forms a second set of cylinders that are self-aligned toa transistor of the second nano-sheet 104 within the cavities in thesame manner described in FIG. 3A above. As explained above, thecylinders of the second set of cylinders that form in the areassurrounding the second nano-sheet 104 and the gates 106 form anuncontrollable “finger print” pattern and are removed in the same mannerdescribed in FIG. 3A above.

In one or more embodiments, unwanted cylinders of the second set ofcylinders may be formed within the cavities and are removed by formingan etch mask and using a lithography process as described in FIG. 3A.

After the unwanted cylinders of the second set of cylinders are removed,the remaining cylinders of the second set of cylinders are metalized,forming a second set of metalized cylinders 124 by either selectivelyremoving the second set of cylinders and forming cylindrical openings,as described in FIG. 1E, and filling the cylindrical openings using ametal deposition process, or using imbedding/infiltration in the samemanner described in FIG. 1F.

After forming the second set of metalized cylinders 124, the matrix 118of the first self-aligning mixture, the matrix material of the secondself-aligning mixture, and the fill material 115 are removed, and theopen areas surrounding the vertical stack comprising the firstnano-sheet 102 and the second nano-sheet 104 are isolated by beingfilled with a filler material 122 in the same manner described in FIG.if. Alternately, in some embodiments, the matrix 118 of the firstself-aligning mixture, the matrix material of the second self-aligningmixture form the isolation of the device and hence are not removed andreplaced with an insulating fill material.

In various embodiments multiple sets of interconnects having differentorientations morphologies, and/or junctions may be formed withinvertical structures comprising multiple stacks of nano-lines (i.e.multiple stacks of nano-sheets or nano-wires). Accordingly, one or moreembodiments will be described using the cross-sectional FIGS. 4A-4Dalong with the flow chart of FIG. 5.

FIGS. 4A-4D illustrate cross-sectional views of a semiconductor deviceduring various stages of fabrication in accordance with an embodiment ofthe present application, wherein FIG. 4A illustrates a cross-sectionalview of the device after forming a second stack of nano-sheets, FIG. 4Billustrates a cross-sectional view of the device after coating thedevice with a second self-assembling polymer mixture, FIG. 4Cillustrates a cross-sectional view the device after causingself-assembly of the second polymer mixture in order to form a secondpattern for interconnects, and FIG. 4D illustrates a cross-sectionalview of the device after metalizing the second pattern for interconnectsto form functional interconnects and isolating the device from adjacentdevices.

Unlike the embodiments described before, embodiments of presentapplication include forming multiple vertical levels of interconnects.As also illustrated in this embodiment, some of the vertical levels ofinterconnects may be formed together in a single DSA process. As anillustration, this embodiment builds on the embodiment described inFIGS. 1A-1F by forming additional vertical levels of interconnectstarting from the structure of FIG. 1F (block 500 of FIG. 5).

In one embodiment, after forming the first set of metalized cylinders123 as described in FIGS. 1A-1F, a second stack of a plurality ofnano-sheets may be formed and a second set of horizontally routedinterconnects may be formed using a second directed-self assemblyprocess, as illustrated in FIGS. 4A-4C.

Advantageously, in one or more embodiments, multiple sets ofinterconnects having different orientations and/or junctions may beformed independently from each other using a separate directedself-assembly processes.

Referring to FIG. 4A and block 502 of FIG. 5, a second stack of aplurality of nano-lines comprising fourth nano-sheets 314 arranged in afourth plane is stacked above third nano-sheets 312 arranged in a thirdplane. The third plane and the fourth plane are arranged in a directionparallel to the working surface of the substrate, and therefore, thefirst nano-sheets 102, the second nano-sheets 104, the third nano-sheets312, and the fourth nano-sheets 314 are all parallel to each other.However, in some embodiments, some of the nano-sheets, for example, thethird nano-sheets 312, and the fourth nano-sheets 314 may be orientedperpendicular to the first nano-sheets 102 and the second nano-sheets104.

In one or more embodiments, the second stack of a plurality ofnano-sheets including the third nano-sheets 312 and the fourthnano-sheets 314 may comprise the same material as the first stack of aplurality of nano-sheets, e.g., the first nano-sheets 102 and the thirdnano-sheets 312 may be the same material.

In various embodiments, as explained above, the third nano-sheets 312and the fourth nano-sheets 314 may be functionalized to have differentdoping or different material, or may be functionalized using a maskingprocess to form interconnects independently as described in FIG. 3.

The third nano-sheets 312 and the fourth nano-sheets 314 are surroundedby gates 303 and include a second plurality of open spaces 318, a secondplurality of outer openings 322, and a third plurality of open spaces320 in a similar manner described in FIG. 1A.

Referring to FIG. 4B, the substrate no is coated with a second polymermixture 324 and fills the second plurality of open spaces 318, the thirdplurality of open spaces 320, the first plurality of outer openings 310,and the second plurality of outer openings 322 in order to form a secondset of interconnects. The second polymer mixture 324 may be a blockcopolymer as described with respect to the polymer mixture 116 describedabove. However, the composition of the second polymer mixture 324 may bedifferent from the composition of the polymer mixture 116.

In one or more embodiments, for illustration, the nano-sheets may befunctionalized in a manner such that the minority polymer (cylinderforming polymer material) is attracted to the third nano-sheets 312 orsecond nano-sheets 104 and the fourth nano-sheets 314 (or vice versa).The actual pattern being formed is therefore quite flexible allowing thedesigner to lay out interconnects in different patterns.

Referring to FIG. 4C and block 504 of FIG. 5, the second polymer mixture324 undergoes microphase separation to form a second set ofself-aligning structures comprising a second set of cylinders 326between the second nano-sheets 104 and the third nano-sheets 312, andbetween the third nano-sheets 312 and the fourth nano-sheets 314 similarto the process described in FIG. 1D above.

The second set of cylinders 326 may self-align to transistors formedwithin the third nano-sheets 312 in both the second plurality of openspaces 318 and the third plurality of open spaces 320 due to how thenano-sheets are functionalized. The second set of cylinders 326 maycomprise the first (minority) polymer of the second polymer mixture 324and are surrounded by a matrix material 325 comprising the second(majority) polymer of the second polymer mixture 324.

In one or more embodiments, as described above, multiple cylinders ofthe second set of cylinders 326 may be formed between the secondnano-sheets 104 and the third nano-sheets 312, and between the thirdnano-sheets 312 and the fourth nano-sheets 314, such that the quantityof cylinders comprising the first set of cylinders 316 and the secondset of cylinders 326 may be different.

Similar to as described above with respect to FIG. 1E, the cylinders ofthe second set of cylinders 326 formed in the first plurality of outeropenings 310 are removed.

Referring to FIG. 4D and block 506 of FIG. 5, the second set ofcylinders 326 are metalized, forming a second set of functionalizedcylinders 327. In one or more embodiments, the second set of cylinders326 may be removed forming cylindrical openings that are filled with ametal using a deposition process in the same manner described andillustrated in FIG. 1F. In one or more embodiments, the second set ofcylinders 326 are metalized via infiltration or embedding as describedin FIG. 1F.

After forming a second set of functionalized cylinders 327, the matrixmaterial 325 of the second polymer mixture 324 is removed in the samemanner described in FIG. 1E, and the second plurality of outer openings322 are isolated by being filled with an insulating filler material 328,for example, as described in FIG. 1F.

Accordingly, FIG. 6 illustrates a cross-sectional view of asemiconductor device during a stage of fabrication in accordance with anembodiment of the present application, wherein FIG. 6 illustrates across-sectional view of the device after global interconnects are formedover vertical stacks of nano-sheets.

Referring to FIG. 6, the open spaces above the fourth nano-sheets 314formed between adjacent gates 303 may be coated with an additionalbilayer di-block copolymer mixture (e.g., in step shown in FIG. 1C or4B), which may also be the overfill in FIG. 1C or 4B. In thisembodiment, the pinning structure formed above the gates 303 and thefourth nano-sheets 314 may enable formation of the interconnect that isoriented perpendicular to the layer below. For example, a subsequentnano-sheet above the fourth nano-sheets 314 may be orientedperpendicular to the fourth nano-sheets 314.

Accordingly, as explained above, for example, a third set of cylinders602 and a fourth set of cylinders 604 that comprise a first polymer ofthe additional bilayer di-block copolymer mixture may be formedorthogonal to each other with the third set of cylinders 602 extendingin directions perpendicular to the nano-sheets and the fourth set ofcylinders 604 formed above the gates 303 in a direction parallel to thenano-sheets formed in a matrix material comprising a second polymer 606of the additional bilayer di-block copolymer mixture. The third set ofcylinders 602 and the fourth set of cylinders 604 may also intersecteach other and may connect in a plurality of locations, forming“T-shaped” junctions. For example, the fourth set of cylinders 604 mayfunction as global interconnects.

The third set of cylinders 602 and the fourth set of cylinders 604 maybe formed and metalized using the directed self-assembly process andmetallization process described in FIGS. 1C-1F as described above.

In various embodiments, as described above, when coating the substratewith a self-aligning polymer mixture, cylinders may also be formedwithin the open areas of the working surface of the substrate 114. Thecylinders formed in open areas of the working surface of the substrate114 may be used to route interconnects between vertically stackednano-sheets or nano-wires that are not perfectly adjacent to one anotherand route interconnects between different levels of different verticalstacks of nano-sheets or nano-wires.

FIGS. 7A-7B illustrate cross-sectional views of a semiconductor deviceduring a stage of fabrication in accordance with an embodiment of thepresent application, wherein FIG. 7A illustrates a top view of thedevice after interconnects are routed between different vertical stacksof nano-sheets or nano-wires across the working surface of thesubstrate, and FIG. 7B illustrates a cross-sectional view of an upwardangled interconnect.

FIG. 7A illustrates a top view of the vertical stack of nano-sheetsformed in FIG. 1. As illustrated in FIG. 7A, the first set of metalizedcylinders 123 formed between vertical stacks of nano-sheets ornano-wires such as the second nano-sheets 104 may be routed in a varietyof orientations and may connect to other functionalized cylindersextending out of other vertical stacks of nano-sheets or nano-wiresformed across the horizontal surface of the substrate 114. For example,in one or more embodiments, a cylinder of the first set of metalizedcylinders 123 aligned to a terminal of a transistor of the secondnano-sheet 104 may be routed to connect to a terminal in a transistor ofa first nano-sheet 102 of another vertical stack of nano-sheets that isnot directionally adjacent across the horizontal plane of the workingsurface of the substrate 114.

In one or more embodiments, where microphase separation is caused bysolvent annealing the portions of the first set of cylinders 120 thatextend out of the plurality of cavities 112 may bend vertically on eachend after they are quenched in the same manner described in FIG. 1Dabove. A cross-sectional view of a metalized cylinder with a verticalbend can be seen in FIG. 7B across the line 7B-7B′ of FIG. 7A.

Referring to FIG. 7B, in one or more embodiments, the portions of themetalized cylinders 123 that extend out of the plurality of cavities 112may form an elbow shape and bend upwards to an angle of 9 degree in oneembodiment. One advantage of this is that is allows for the formation ofinterconnects between transistors of different nano-sheets within thesame vertical stack of nano-sheets and/or the formation of interconnectswithin the same vertical stack of nano-sheets that connect verticallyand eventually connect to a global interconnect formed above thevertical stacks of nano-sheets as described in FIG. 6. Accordingly,embodiment of the present application also include forming a physicalcontact, i.e., an electrical connection to another interconnect.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

Example embodiments of the present invention are summarized here. Otherembodiments can also be understood from the entirety of thespecification and the claims filed herein.

Example 1. A method of forming a device, the method including: receivinga substrate having nano-channels positioned over the substrate andextending in a direction parallel to a working surface of the substrate,the nano-channels arranged so that first nano-channels are positionedvertically above second nano-channels in a vertical stack, thenano-channels having a gate formed all around a cross section of thenano-channels; depositing a polymer mixture on the substrate that fillsopen spaces around the nano-channels; causing self-assembly of thepolymer mixture resulting in forming polymer cylinders extendingparallel to the working surface of the substrate and perpendicular tothe nano-channels; and metalizing the polymer cylinders sufficient tocreate an electrical connection to terminals of the nano-channels. Themethod may further include metalizing the polymer cylinders sufficientto create an electrical connection to another interconnect. As describedin various embodiment, this process may be selectively performed by theuse of pinning structures (designed cavities) provided by the 3-Dstructure of the device being fabricated.

Example 2. The method of example 1, where causing self-assembly of thepolymer mixture includes forming first cylinders and second cylinders,the first cylinders formed of a first material while the secondcylinders are formed of a second material, the first and second materialbeing different.

Example 3. The method of one of examples 1 or 2, where metalizing thepolymer cylinders include causing a first metal to infiltrate materialof the polymer cylinders.

Example 4. The method of one of examples 1 to 3, where a second polymerfrom the polymer mixture occupies space around the cylinders, and wheremetalizing the polymer cylinders include removing the polymer cylindersand replacing with a first metal.

Example 5. The method of one of examples 1 to 4, where the polymercylinders extend into an adjacent trench.

Example 6. A method of forming a device, the method including: receivinga substrate having a three dimensional (3D) structure including aplurality of nano-sheets, a plurality of walls, and a plurality ofcavities, one of the plurality of nano-sheets including a first sheetseparated from a second sheet of the plurality of nano-sheets in a firstdirection by one of the plurality of cavities, the plurality ofnano-sheets being supported by the plurality of walls, the plurality ofnano-sheets extending along a second direction orthogonal to the firstdirection, the first sheet being spaced apart from a third sheet of theplurality of nano-sheets along a horizontal plane in a third directionthat is orthogonal to both the first and the second directions; andforming a plurality of cylindrical interconnects within the 3D structurewith a directed self assembly process, where each of the plurality ofcavities includes one of the plurality of cylindrical interconnects.

Example 7. The method of example 6, where forming the plurality ofcylindrical interconnects includes: performing a solvent annealingprocess to form a first interconnect extending in the first direction, asecond interconnect extending in the second direction, and a thirdinterconnect extending in the third direction, the first interconnect,the second interconnect, and the third interconnect being electricallycoupled to each other.

Example 8. The method of one of examples 6 or 7, where forming theplurality of cylindrical interconnects includes: filling the pluralityof cavities with a polymer mixture including a block copolymer;converting the polymer mixture to form a plurality of polymer cylinders,where each of the plurality of cavities includes one of the polymercylinders; and metalizing the plurality of polymer cylinders.

Example 9. The method of one of examples 6 to 8, where forming theplurality of cylindrical interconnects includes: selectively contactingeach of the plurality of polymer cylinders with a selected one of theplurality of nano-sheets; or selectively contacting one of the pluralityof polymer cylinders with another interconnect within the 3D structure.

Example 10. The method of one of examples 6 to 9, where the selectivelycontacting includes having functionalized nano-sheets within theplurality of nano-sheets and preferentially attracting the plurality ofpolymer cylinders during the directed self assembly process towards thefunctionalized nano-sheets.

Example 11. The method of one of examples 6 to 10, where the pluralityof polymer cylinders include a first set of polymer cylinders includinga first polymer material and a second set of polymer cylinders includinga second polymer material, the first polymer material being a differentpolymer material than the second polymer material.

Example 12. The method of one of examples 6 to 11, where metalizing theplurality of polymer cylinders further includes infiltrating a metalinto the plurality of polymer cylinders.

Example 13. The method of one of examples 6 to 12, where the pluralityof polymer cylinders include a first polymer material that is surroundedby a second polymer material, and where metalizing the polymer cylindersfurther includes removing the plurality of polymer cylinders forming aplurality of cylindrical openings, and filling the plurality ofcylindrical openings with a metal.

Example 14. A method of forming a device, the method including: forminga first stack of plurality of nano-lines over a substrate, the firststack of plurality of nano-lines including first nano-lines arranged ina first plane above the substrate and second nano-lines arranged in asecond plane above the first plane; and forming a first set of polymercylinders between the first nano-lines and the second nano-lines with afirst directed self-assembly process.

Example 15. The method of example 14, where the first directedself-assembly process further includes: filling a cavity between thefirst plane and the second plane with a first polymer mixture includinga di-block copolymer; converting the first polymer mixture to form thefirst set of polymer cylinders; and metalizing the first set of polymercylinders.

Example 16. The method of one of examples 14 or 15, further including:forming a second stack of plurality of nano-lines over the first stackof plurality of nano-lines, the second stack of plurality of nano-linesincluding third nano-lines arranged in a third plane above the secondplane and fourth nano-lines arranged in a fourth plane above the thirdplane; and forming a second set of polymer cylinders between the thirdnano-lines and the fourth nano-lines with a second directedself-assembly process.

Example 17. The method of one of examples 14 to 16, where the seconddirected self-assembly process further includes: filling a cavitybetween the third plane and the fourth plane with a second polymermixture including a multi-block copolymer; and converting the secondpolymer mixture to form the second set of polymer cylinders; andmetalizing the second set of polymer cylinders.

Example 18. The method of one of examples 14 to 17, further including:forming the second stack of plurality of nano-lines over the first stackof plurality of nano-lines prior to forming the first set of polymercylinders, the second stack of plurality of nano-lines including thirdnano-lines arranged in a third plane above the second plane and fourthnano-lines arranged in a fourth plane above the third plane; filling afirst cavity between the first plane and the second plane and a secondcavity between the third plane and the fourth plane with a polymermixture including a multi-block copolymer; converting the polymermixture to form the first set of polymer cylinders including a firstpolymer material between the first plane and the second plane and asecond set of polymer cylinders including a second polymer materialbetween the second plane and the third plane; and metalizing the firstset of polymer cylinders and the second set of polymer cylinders.

Example 19. The method of one of examples 14 to 18, where the first setof polymer cylinders is oriented orthogonal to the second set of polymercylinders.

Example 20. The method of one of examples 14 to 19, where the first setof polymer cylinders is attached to the second set of polymer cylindersat a plurality of locations.

What is claimed is:
 1. A method of forming a device, the methodcomprising: receiving a substrate having nano-channels positioned overthe substrate and extending in a direction parallel to a working surfaceof the substrate, the nano-channels arranged so that first nano-channelsare positioned vertically above second nano-channels in a verticalstack, the nano-channels having a gate formed all around a cross sectionof the nano-channels; depositing a polymer mixture on the substrate thatfills open spaces around the nano-channels; causing self-assembly of thepolymer mixture resulting in forming polymer cylinders extendingparallel to the working surface of the substrate and perpendicular tothe nano-channels; and metalizing the polymer cylinders sufficient tocreate an electrical connection to terminals of the nano-channels. 2.The method of claim 1, wherein causing self-assembly of the polymermixture comprises forming first cylinders and second cylinders, thefirst cylinders formed of a first material while the second cylindersare formed of a second material, the first and second material beingdifferent.
 3. The method of claim 1, wherein metalizing the polymercylinders include causing a first metal to infiltrate material of thepolymer cylinders.
 4. The method of claim 1, wherein a second polymerfrom the polymer mixture occupying space around the cylinders, andwherein metalizing the polymer cylinders include removing the polymercylinders and replacing with a first metal.
 5. The method of claim 1,wherein polymer cylinders extend into an adjacent trench.
 6. A method offorming a device, the method comprising: receiving a substrate having athree dimensional (3D) structure comprising a plurality of nano-sheets,a plurality of walls, and a plurality of cavities, one of the pluralityof nano-sheets comprising a first sheet separated from a second sheet ofthe plurality of nano-sheets in a first direction by one of theplurality of cavities, the plurality of nano-sheets being supported bythe plurality of walls, the plurality of nano-sheets extending along asecond direction orthogonal to the first direction, the first sheetbeing spaced apart from a third sheet of the plurality of nano-sheetsalong a horizontal plane in a third direction that is orthogonal to boththe first and the second directions; and forming a plurality ofcylindrical interconnects within the 3D structure with a directed selfassembly process, wherein each of the plurality of cavities comprisesone of the plurality of cylindrical interconnects.
 7. The method ofclaim 6, wherein forming the plurality of cylindrical interconnectscomprises: performing a solvent annealing process to form a firstinterconnect extending in the first direction, a second interconnectextending in the second direction, and a third interconnect extending inthe third direction, the first interconnect, the second interconnect,and the third interconnect being electrically coupled to each other. 8.The method of claim 6, wherein forming the plurality of cylindricalinterconnects comprises: filling the plurality of cavities with apolymer mixture comprising a block copolymer; converting the polymermixture to form a plurality of polymer cylinders, wherein each of theplurality of cavities comprises one of the polymer cylinders; andmetalizing the plurality of polymer cylinders.
 9. The method of claim 8,wherein forming the plurality of cylindrical interconnects comprises:selectively contacting each of the plurality of polymer cylinders with aselected one of the plurality of nano-sheets; or selectively contactingone of the plurality of polymer cylinders with another interconnectwithin the 3D structure.
 10. The method of claim 8, wherein theselectively contacting comprises having functionalized nano-sheetswithin the plurality of nano-sheets and preferentially attracting theplurality of polymer cylinders during the directed self assembly processtowards the functionalized nano-sheets. ii. The method of claim 8,wherein the plurality of polymer cylinders comprise a first set ofpolymer cylinders comprising a first polymer material and a second setof polymer cylinders comprising a second polymer material, the firstpolymer material being a different polymer material than the secondpolymer material.
 12. The method of claim 8, wherein metalizing theplurality of polymer cylinders further comprises infiltrating a metalinto the plurality of polymer cylinders.
 13. The method of claim 8,wherein the plurality of polymer cylinders comprise a first polymermaterial that is surrounded by a second polymer material, and whereinmetalizing the polymer cylinders further comprises removing theplurality of polymer cylinders forming a plurality of cylindricalopenings, and filling the plurality of cylindrical openings with ametal.
 14. A method of forming a device, the method comprising: forminga first stack of plurality of nano-lines over a substrate, the firststack of plurality of nano-lines comprising first nano-lines arranged ina first plane above the substrate and second nano-lines arranged in asecond plane above the first plane; and forming a first set of polymercylinders between the first nano-lines and the second nano-lines with afirst directed self-assembly process.
 15. The method of claim 14,wherein the first directed self-assembly process further comprises:filling a cavity between the first plane and the second plane with afirst polymer mixture comprising a di-block copolymer; converting thefirst polymer mixture to form the first set of polymer cylinders; andmetalizing the first set of polymer cylinders.
 16. The method of claim14, further comprising: forming a second stack of plurality ofnano-lines over the first stack of plurality of nano-lines, the secondstack of plurality of nano-lines comprising third nano-lines arranged ina third plane above the second plane and fourth nano-lines arranged in afourth plane above the third plane; and forming a second set of polymercylinders between the third nano-lines and the fourth nano-lines with asecond directed self-assembly process.
 17. The method of claim 16,wherein the second directed self-assembly process further comprises:filling a cavity between the third plane and the fourth plane with asecond polymer mixture comprising a multi-block copolymer; andconverting the second polymer mixture to form the second set of polymercylinders; and metalizing the second set of polymer cylinders.
 18. Themethod of claim 14, further comprising: forming the second stack ofplurality of nano-lines over the first stack of plurality of nano-linesprior to forming the first set of polymer cylinders, the second stack ofplurality of nano-lines comprising third nano-lines arranged in a thirdplane above the second plane and fourth nano-lines arranged in a fourthplane above the third plane; filling a first cavity between the firstplane and the second plane and a second cavity between the third planeand the fourth plane with a polymer mixture comprising a multi-blockcopolymer; converting the polymer mixture to form the first set ofpolymer cylinders comprising a first polymer material between the firstplane and the second plane and a second set of polymer cylinderscomprising a second polymer material between the second plane and thethird plane; and metalizing the first set of polymer cylinders and thesecond set of polymer cylinders.
 19. The method of claim 18, wherein thefirst set of polymer cylinders is oriented orthogonal to the second setof polymer cylinders.
 20. The method of claim 18, wherein the first setof polymer cylinders is attached to the second set of polymer cylindersat a plurality of locations.